For detecting transmission errors occurring on high speed signal lines, a standard for future graphic memory systems (e.g., the Graphic Double Data Rate 5 (GDDR5) standard) envisages an error detection on the data bus to improve system reliability. As graphics systems store more and more code in the DRAM, effective error detection becomes essential, as random bit fails associated with any high speed data transmission would lead to unacceptable system failures.
In the GDDR5 standard, the transmitted data is secured using a CRC (cyclic redundancy check) with an algorithm that is well established within high quality communication environments like ATM networks. The algorithm enables a detection of most errors with 100% probability. Error detection can be used to trigger retraining of the data transmission line which allows the system to dynamically adapt to changing conditions (e.g., temperature or voltage drift).
Until now, such memory systems have not provided the ability to detect errors in the transmitted addresses without using an additional pin at the controller module and/or the memory module. Such an additional pin can be used for transmitting a so-called parity bit which can be used for detecting an error in the transmitted address. However the additional pin at the controller module and/or the memory module disadvantageously increases the pin count as well as the power consumption at the controller module and/or the memory module.
It is therefore desirable to achieve improved error detection by means of a cyclic redundancy check when data and addresses are transferred between a memory and a controller which also allows recognition of an error in the transferred address.